This application claims the priority of Korean Patent Application No. 2002-59412, filed Sep. 30, 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to shielding a data line to prevent coupling in a synchronous dynamic random access memory (SDRAM).
2. Description of the Related Art
As the operating speed and the integration density of the SDRAM increase, the number of data input/output pins increases. An increase in the amount of data input or output at any given time requires an increase in the number of data buses for transmitting the data.
Increases in the number of data buses and noise due to a rapid operating speed increase the interference between data buses or between a data bus and other signal lines. Consequently, it becomes important to minimize the interference in the SDRAM.
In a conventional SDRAM, lines of a supply voltage and a ground voltage are placed on both sides of the data bus, and thus the data bus is shielded so as to prevent abnormal operations due to the coupling between the data buses.
FIG. 1 is a view illustrating shielding of a data bus in an SDRAM according to prior art. Referring to FIG. 1, a voltage line 120, which is connected with a supply voltage or a ground voltage VSS, is placed to separate data bus 110 which is to be shielded. That is, the voltage line 120 is used as a shielding line to prevent coupling between data buses 110 that are adjacent to each other.
As a bit configuration of the SDRAM becomes more complicated, the number of data bus lines increases, and thus the area of a layout of the SDRAM greatly increases. The bit configuration indicates a number of data bits which can be input or output to or from the SDRAM at a time. For example, the bit configuration of the SDRAM which inputs or outputs 4 bits of data is 4, and the bit configuration of the SDRAM which inputs or outputs 8 bits of data is 8. In general, the bit configuration is represented as X4, X8, X16, or the like.
The SDRAM is usually designed to operate in various bit configuration modes, and the bit configuration mode can be reset to a certain desired bit configuration after manufacture of the SDRAM is completed. In addition, the SDRAM can operate in a single data rate (SDR) mode where the SDRAM outputs a bit of data per pin during one clock cycle, or in a double data rate (DDR) mode where the SDRAM outputs two bits of data per pin during one clock cycle.
As for the DDR SDRAM, if the bit configuration is X4, eight data bus lines are employed, and if the bit configuration is X16, 32 data bus lines are employed.
Thus, when the data bus is shielded as shown in FIG. 1, eight data buses and nine power lines are required in an X4 bit configuration, and 32 data bus lines and 33 power supply lines are required in an X16 bit configuration. Consequently, the area of the layout of the SDRAM increases, which causes the increase in size of an SDRAM chip.